I'm writing NES emulator (it's name is 'NEZ' for now) and I don´t have very much experience in this, so please be patient. I´ve got a couple of very simple demos to work perfectly (like: mmx, jumpy, zelda titlescreen, macos...) with correct colors and all (a bit slow though). But if the demo uses NMI interrupts (like: billworld01, blocks, sprite...) it crashes, because I don't know how to implement it in my CPU...

I believe it works like this: When the PPU generates a Vertical Blanking Impulse, the program counter jumps to the adresse 0xFFFA, and continues from there. I guess the code uses a RTI or RTS or something to get back to where it was before.

Now how am I supposed to implement that? Should I let the CPU make a NMI interrupt right after I've updated the screen? Only once? What does Non-Msakable Interrept mean? How many cycles should I add to the counter? Does the NMI clear D7 in $2002? Does NMI trigger after every screen refresh (60 times per second)? Am I supposed to push the program counter onto the stack? The questions goes on forever... It feels and sounds like a simple thing, but I just can't make it work. I have only found little information about this. I would appreciate if someone tells me or give me a link to an accurate document...

// Zansibal

The NMI means what it says, it cannot be masked out by the I flag like the IRQ.

It is generated by the PPU every frame sometime after the last visible line, IF bit 7 of the PPU control register 1 ($2000) is set. And it doesn't clear bit 7 of $2002, a read from it does.

When the CPU receives a NMI signal, it first pushes the program counter (PC) and the status reg on the stack.
After that, it READS an address from $FFFA and loads it into the PC, it doesn't jump there! Which means if $8010 is stored at $FFFA, it jumps to $8010.
When the NMI routine is done it should run a RTI (return from interrupt).
Jumping into NMI take 7 CPU cycles totally.

You can read about it in NESTECH.TXT and any 6502 document.

thank you, I think you have covered most of my questions... I'll return with new questions if I can't make it work. I think I never tried to push the CPU status reg onto the stack as well...
wish me luck
Zansibal

I got the NMI interrupt working a while ago, thanks to your info, Jsr.
But when I was reading about the IRQ interrupt, I saw the following (from YOSHis NESTECH.txt)

"IRQ/BRK is triggered under two circumstances, hence it's split name:
when a software IRQ is executed (the BRK instruction), or when a
hardware IRQ is executed (via the IRQ line)."

I know about the software BRK command, but what does he mean by the hardware IRQ executed via the IRQ line. Is there a thing in the CPU that generate this IRQ regulary or at any other moments? Please tell me if you know..

//Zansibal

YOSHi did write NESTECH, didn´t he? (I just couldn´t find any name in the file)

The IRQ is another interrupt, like the NMI. But the CPU is ignoring this if the I flag in the status reg is set.

Some cartridges have hardware to generate IRQs, like the MMC3. SMB 3 uses it to draw the bottom status bar.
IRQs can also be triggered by the APU, like when it has finished playing a DMC stream.

thank you... I don't think I have to worry about that for a while then