Alright, I'm looking at the specs for MMC1 (#1) in that viewer app you can download from this website, and I want to see if I can clarify some things:

1) I noticed that there is a range of addresses you can write to for a register, like for example register 0 spans 8000-9fff. What would be the difference, if, say, I write to 81af instead of 9b25?

2) There seems to be a diffrence between a 512k cart and a 1024 cart. How would I determine that for the emulator/NES?

3) I know I write to bit 7 of register 0 to reset the port, but would be the process, in which I would do that?

4) For register 1, bits 0-3, is that value merely the page number, which would be in a formula like this:

(starting spot in CHR-ROM) = (size of ROM area) * (page number)/(total number of pages)

with

(total number of pages) = (size of ROM area) / (size of each page)

?

5) What is this 256k PRG-ROM bank selection?

6) What is this about MMC1 registers reading only 1 bit at a time and values not being used until the entire 5-bit array is filled. Then it says that it can be reset (quod vide question 3) What does this imply? It also says that it has only one 5-bit array "for this data." This utterly confusing. Should I worry about it?

Thanks for taking the time in reading (and hopefully answering) my questions. I shall now sit back and await your replies.

Thanks.

^_^

1. no difference, it will look exactly the same to the mapper.

2. I don't think there is a 1024KB MMC1 game. Dragon Warrior 4 was thought to be that size, but it was a bad dump. (it's 512KB)

3. Just write it like a normal register (LDA #$80 / STA $8000), it's seperate from the port.

4. It selects 4KB or 8KB banks. Just experiment with it a bit and you'll see how it works. I usually use CHR-RAM, so I don't know.

5. I'm not sure why it's called that. Should be safe to consider it the MSB of the PRG bank select (for a 512KB ROM).

6. It's pretty simple, really. First, you'd write #$80 to reset it, then take your 5-bit value and write it into bit 0 of the register, one bit at a time.

The port is shared between all the registers, but that only means you need to completely write one register before moving on to reset and write the next one.

I used the MMC1 once, here's the routine I used to write to the registers (reg0 and reg3 are bytes in RAM containing the 5-bit value):

mmc1write:
lda #$80
tax
sta $8000, x
lda reg0
tax
sta $8000, x
lsr
tax
sta $8000, x
lsr
tax
sta $8000, x
lsr
tax
sta $8000, x
lsr
tax
sta $8000, x

lda #$80
tax
sta $E000, x
lda reg3
tax
sta $E000, x
lsr
tax
sta $E000, x
lsr
tax
sta $E000, x
lsr
tax
sta $E000, x
lsr
tax
sta $E000, x
rts

Why the heck did I do so many TAX instructions, bus conflict paranoia? :S
But that's what I used a couple years ago, and it works. Also, if you're putting it on a cart eventually, be aware that there are various revisions of MMC1. (MMC1a selects a random 32KB bank at startup.. I dunno about the others)

> 1) I noticed that there is a range of addresses you can write to for a register, like for example register 0 spans 8000-9fff. What would be the difference, if, say, I write to 81af instead of 9b25?

Absolutely no difference at all. The chip simply performs incomplete address decoding (i.e. it only needs to watch 2 address lines instead of 16).

> 2) There seems to be a diffrence between a 512k cart and a 1024 cart. How would I determine that for the emulator/NES?

There is no such thing as 1024KB MMC1 cartridge. The only existing '1024KB MMC1 game' is Dragon Warrior 4, which is really only 512KB (the 1024KB dump is bad, and most of the banks are jumbled around so truncating it is not sufficient).

> 3) I know I write to bit 7 of register 0 to reset the port, but would be the process, in which I would do that?

LDA #$80
STA $8000

> 4) For register 1, bits 0-3, is that value merely the page number?

Yes.

> (starting spot in CHR-ROM) = (size of ROM area) * (page number)/(total number of pages)

Almost - the total number of pages is irrelevant, other than making sure your page number doesn't exceed it (if it does, you just ignore the high order bit).

> 5) What is this 256k PRG-ROM bank selection?

It's something unique to the NES-SVROM board, where it uses the upper (4th) bit of the CHR ROM select register[s] to select a 256KB PRG ROM bank. This is because the MMC1 is normally only capable of addressing 256KB of PRG ROM *total*, so they just stole one of the CHR bits to increase it to 512KB. Another board, NES-SOROM, does something similar but instead uses the bit to select an additional bank of SRAM.

> 6) What is this about MMC1 registers reading only 1 bit at a time and values not being used until the entire 5-bit array is filled.

The MMC1 only has two input lines: D0 (serial data) and D7 (reset). You basically write to an MMC1 register 5 times in a row, shifting your value to the right each time so it picks up the next bit.

> Then it says that it can be reset (quod vide question 3) What does this imply?

If you write to the reset bit (i.e. any value with D7 set), the shift counter will be reset to the beginning so it's guaranteed that exactly 5 writes will update a register.

> It also says that it has only one 5-bit array "for this data." This utterly confusing. Should I worry about it?

Yes. Whenever you write to anywhere in $8000-$FFFF, you shift D0 (the bottom bit) into a 5-bit register. On the 5th write, you transfer the contents of that temporary register into the appropriate MMC1 register (selected according to where you wrote). Incidentally, this means that only the location of the *last* write matters.

Here's some example code (pretty much taken directly from my mapper DLLs) for handling MMC1 writes:

void __cdecl MMC1_Write (int Bank /*0x8..0xF*/, int Addr /*0x000..0xFFF*/, int Val /*0x00..0xFF*/)
{
uint8 Reg = (Bank >> 1) & 3;
if (Val& 0x80)
{
MMC1.Latch = MMC1.LatchPos = 0;
return;
}
MMC1.Latch |= (Val & 1) << MMC1.LatchPos++;
if (MMC1.LatchPos == 5)
{
MMC1.Regs[Reg] = MMC1.Latch & 0x1F;
MMC1.Latch = MMC1.LatchPos = 0;
MMC1.Sync(); // update mirroring and PRG/CHR banks - you can also just switch (Reg) { ... } and update whatever was affected
}
}


--
Quietust
P.S. If you don't get this note, let me know and I'll write you another.

I tried it out, but I can't get it to swap out:

; MMC1 test

.inesprg 03
.ineschr 01
.inesmir 00
.inesmap 01

.code
.org $8000

paldata: .db $0f

.bank 1
.org $8000

paldata2: .db $28

.bank 2
.org $C000

wait_vblank:
pha
wait_affcon:
lda $2002
bpl wait_affcon
pla
rts

irqbrknmi:
rti

main:
sei
cld

ldx #$ff
txs

inx
txa
tay

clearzp:
sta <$00, x
inx
bne clearzp

stx <$00
inx
stx <$01

ldx #$07

clearurom:
sta [$00], y
iny
bne clearurom
ldy <$01
iny
sty <$01
tay
dex
bne clearurom

jsr wait_vblank

sta $2000
sta $2001

lda #$20
sta $2006
sty $2006
tya

ldx #$08

clearppu:
sta $2007
iny
bne clearppu
dex
bne clearppu

screen_changer:
lda $2002
tya

iny
sty $4016
sta $4016
ldy #$08

check_buttons:
lda $4016
and #$01
sta <$02, x
inx
dey
bne check_buttons

lda #$80
sta $8000

lda #$0e
ldx #$05

write_register0:
sta $8000
lsr A
dex
bne write_register0

lda #$80
sta $e000

lda <$02
bne abutton
lda <$03
bne bbutton

abutton:
lda #$00
sta <$10
jmp mapswap

bbutton:
lda #$01
sta <$10

mapswap:
lda <$10
ldy #$05

do_swap:
sta $e000
lsr a
dey
bne do_swap

lda #$3f
sta $2006
tya
sta $2006

ldx #$20

loadpal:
lda paldata
sta $2007
dex
bne loadpal

jmp screen_changer

.bank 3
.org $FFFA

.dw irqbrknmi
.dw main
.dw irqbrknmi

.bank 4
.incbin "blank.chr"

i'm sure there's 2 nesasm banks to 1 prgrom bank so you would have 6 banks + 1 chrrom bank - so have you tried this with your .bank 3 set to a higher num and .bank 4 set to 7