> 1) I noticed that there is a range of addresses you can write to for a register, like for example register 0 spans 8000-9fff. What would be the difference, if, say, I write to 81af instead of 9b25?

Absolutely no difference at all. The chip simply performs incomplete address decoding (i.e. it only needs to watch 2 address lines instead of 16).

> 2) There seems to be a diffrence between a 512k cart and a 1024 cart. How would I determine that for the emulator/NES?

There is no such thing as 1024KB MMC1 cartridge. The only existing '1024KB MMC1 game' is Dragon Warrior 4, which is really only 512KB (the 1024KB dump is bad, and most of the banks are jumbled around so truncating it is not sufficient).

> 3) I know I write to bit 7 of register 0 to reset the port, but would be the process, in which I would do that?

LDA #$80
STA $8000

> 4) For register 1, bits 0-3, is that value merely the page number?

Yes.

> (starting spot in CHR-ROM) = (size of ROM area) * (page number)/(total number of pages)

Almost - the total number of pages is irrelevant, other than making sure your page number doesn't exceed it (if it does, you just ignore the high order bit).

> 5) What is this 256k PRG-ROM bank selection?

It's something unique to the NES-SVROM board, where it uses the upper (4th) bit of the CHR ROM select register[s] to select a 256KB PRG ROM bank. This is because the MMC1 is normally only capable of addressing 256KB of PRG ROM *total*, so they just stole one of the CHR bits to increase it to 512KB. Another board, NES-SOROM, does something similar but instead uses the bit to select an additional bank of SRAM.

> 6) What is this about MMC1 registers reading only 1 bit at a time and values not being used until the entire 5-bit array is filled.

The MMC1 only has two input lines: D0 (serial data) and D7 (reset). You basically write to an MMC1 register 5 times in a row, shifting your value to the right each time so it picks up the next bit.

> Then it says that it can be reset (quod vide question 3) What does this imply?

If you write to the reset bit (i.e. any value with D7 set), the shift counter will be reset to the beginning so it's guaranteed that exactly 5 writes will update a register.

> It also says that it has only one 5-bit array "for this data." This utterly confusing. Should I worry about it?

Yes. Whenever you write to anywhere in $8000-$FFFF, you shift D0 (the bottom bit) into a 5-bit register. On the 5th write, you transfer the contents of that temporary register into the appropriate MMC1 register (selected according to where you wrote). Incidentally, this means that only the location of the *last* write matters.

Here's some example code (pretty much taken directly from my mapper DLLs) for handling MMC1 writes:

void __cdecl MMC1_Write (int Bank /*0x8..0xF*/, int Addr /*0x000..0xFFF*/, int Val /*0x00..0xFF*/)
{
uint8 Reg = (Bank >> 1) & 3;
if (Val& 0x80)
{
MMC1.Latch = MMC1.LatchPos = 0;
return;
}
MMC1.Latch |= (Val & 1) << MMC1.LatchPos++;
if (MMC1.LatchPos == 5)
{
MMC1.Regs[Reg] = MMC1.Latch & 0x1F;
MMC1.Latch = MMC1.LatchPos = 0;
MMC1.Sync(); // update mirroring and PRG/CHR banks - you can also just switch (Reg) { ... } and update whatever was affected
}
}


--
Quietust
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