There's a few points I'd like to get clear on Kevin's MMC3 IRQ document. His doc has many contradictions (or it's just myself!?).

First, and very firsty... The IRQ counter is _NOT_ always counting down. The IRQ decrements if bits 3 or 4 of 2001h (_not_ 2000h) are enabled, *plus* if out of VBlank period.
Second... "There's no direct access to IRQ counter"... What about C001h? It states that IRQ counter is cleared and reloaded (?) on "next rising edge of PPU A12". What an C001h access _does_???
Third, the IRQ triggering. When the counter reaches zero, an IRQ is triggered on "next rising...etc" _if_ the E001h set the IRQ flag to 1 ???
Next, if the IRQ changes from non-zero to zero (under which situations, for example? C001h?), what happens? IRQ clear to get triggered on "next rising..."?

-Fx3