>pin 14: PRG R/W
>when it's set, the CPU is reading or writing to memory?

When 0 (or low loglc level), this is the bus write cycle. That is, the CPU puts it's own data on the bus intended to be written to some address. Of course, when this signal is 1, the CPU is reading data off the bus. Note that the / is placed before the "W". This is how you can remember that the write operation occurs when R/W is 0 (more info on using the "/" is as follows).

A slash ("/") before the signal name indicates that the signal is active when 0 (a low logic level; as opposed to an implied high (1) one, were the slash absent). Generally a horizontal bar is drawn over the signal name to represent negation, but in ASCII this is hard to do, so a slash is used.


>pin 50: PRG /CE (/A15 & /M2)
>I do not yet know what /CE is. Or /M2. A15 would be for accessing memory higher than $7FFF, right? Because the NES only 'sees' 32K of PRG-ROM, I wouldn't think it's state would ever change, as far as a mapper is concerned.

First, "M2" stands for phi 2, which is simply the 2A03's 1.79 MHz clock. The signal is primarially used as a bus enable line (when it's 1, this instructs data to be read/driven onto the bus. While 0, it indicates that the bus is at rest), which is why you see it combined with A15 (Kevin's document is incorrect here- the logical operation between these two signals is actually (/A15 OR /M2))- it's the NES's built-in poorman's PRG-ROM address decoder (poorman's since it doesn't differentiate between read or write cycles). Mappers like the MMC5 (which can map ROM into 6000-FFFF) have little use for the (/A15 OR /M2) line, since this decoded address range doesn't include 6000-7FFF. Strictly speaking, the M2 line has little merit for CPU read cycles, but for write cycles, it is required to instruct latches to latch data present on the bus before the CPU changes the address bus lines (which will happen before the CPU disables the R/W line).

/CE stands for Chip Enable (or Chip Select), and enables the ROM and it's bus drivers. Output Enable (/OE, if present) simply enables the ROM's bus drivers. Basically these two signals do the same thing on ROMs (and both have to be enabled for the ROM to drive data onto it's bus pins), with the difference that the /CE line puts the ROM into a low power mode, making the ROM's power consumption very low (almost 0). BTW, the access time that ROMs (and RAMs) are designated with, is the time between the activation of the /CE line, and when valid data appears on the ROM's data pins. Now, using /OE to drive the ROM's data onto the bus is faster than using /CE, but since the NES's CPU (and even PPU) buses are so slow, it really doesn't matter what lines you used here.

/CE on RAM chips is used as a general enable, and permits chip read or write actions to occur (providing the /RD or /WR lines are activated. In the case /RD and /WR are enabled simultaniously, /RD has priority. This is how the NES's WRAM is being used: /OE is hardwired active, /WR is tied to the CPU's R/W line, and the /CE line is attached to the NES's poorman's address decoder circuitry for 0000-1FFF).

A0-A15 is simply the direct binary representation of which address the CPU is currently accessing. So in answer to your question, A15 is activated for address in the 8000-FFFF range.


>pins 21 & 56
>CHR's /RD & /WR lines are seperate? I'm guessing it's that way so CHR-RAM can be used. (as opposed to having them on the same pin like PRG, which was always read-only)

They are seperate. This eliminates the need for a bus enable line (M2) like the CPU has. Infact, if the CPU used this convention (instead of the R/W & M2 control lines), the bus contention problems which were present in all the simple mapper types (with the exception of the ANROM) would have never been an issue (the ANROM is immune since it contains extra circuitry to decode exclusive CPU write cycles- somthing which the PPU offers for free).


>With PRG R/W on the same pin, how then is a read access to ROM distinguished from a write? By looking for specific conditions on the address and data bus, perhaps?

conditions are as follows:
-------------------------

/M2 R/W CPU data bus state
--- --- ------------------
0 x floating/disabled
1 0 write
1 1 read

Again, since the R/W line isn't used in Nintendo's cheap built-in PRG-ROM decoder circuitry (/M2 OR /A15), there is no destinction between read or write cycles to PRG-ROMs that use this raw 8000-FFFF decode line (unless extra logic is used to gate R/W with this signal like the ANROM uses (MMCs use a different technique to accomplish this)).

Also, M2 is the 6502's clock signal, and this means that the bus is enabled EVERY single clock cycle. This is why the 6502 had to be designed to make extra reads or writes to redundant addresses during execution of instructions where internal pipelines had to be resolved (like when effective address calculations cross page bounaries, or during any read-modify-write instructions).


hope that helps.


- BT