> See my previous post on this subject.
> But just to be clear, the PPU & CPU buses have mutually exclusive memory
> access cycles (2.68 MHz for PPU; 1.79 MHz for CPU). So there would be no way
> of sharing a common bus between the PPU & CPU (espically since there ARE
> cycles when both the PPU & CPU disable their respective bus read enable
> control lines simultaniously).
Please correct me if I'm wrong, but shouldn't it nevertheless be possible to emulate a dual-port SRAM chip that could function as *both* CPU-memory and PPU-memory by using a single large fast SRAM chip along with equally fast buffering logic that could handle the accesses made by the CPU and the PPU?
Since the PPU runs at 21.47727Mhz (on an NTSC NES), the maximum number of nanoseconds between accesses to this general-purpose memory would be 1 / 21.47727*10^6 = 46.7 ns. Today we have SRAMs with access times as fast as 20 ns. So if such an SRAM chip was used, it could be accessed on *every* CLK cycle generated by the main clock. So if the CPU would read/write the memory during the exact same CLK cycle when the PPU is reading it, then the PPU would be favored and get its data immediately as usual, while the CPU's read/write would be buffered and delayed until the next CLK clock, when the PPU would no longer access the memory. Considering that the M2 clock is either 1/12th or 1/16th of the main CLK clock, shouldn't the CPU get its read data in time if only the buffering logic used would be fast enough?...
// Michel Iwaniec (firstname.lastname@example.org)