>It stands for "phi 2", and represents the NES's raw 1.79 MHz CPU clock signal
>(I have no idea why Kevin abbreviated it "M2"). The duty cycle is 62.5%, and
>is used as the 6502's bus enable line (active when 1). The use of this signal
>is required to allow the 6502 address lines (& the deocders) time to set up
>the next valid address before the address line data can be considered stable.

So you're saying, the time I have to decode the address and respond with data is:
(1/1.79MHz)*0.625 = 349 ns

Correct?

Thanks, its nice to know what limits the designs need to stay under.