As most of you probably know, there are plenty of patents available that document NES hardware and peripherals. Some of the patents contain very useful information. I remember even seeing hardware schemantics about MMC1 in one patent. Patents can be easily downloaded from, for example, US Patent Office's home site (http://www.uspto.gov/) - please tell me if you know any better place.

Anyway, wouldn't it be possible to have the patent docs on nesdev.parodius.com? Even if not, one could still list the patent names (and description of their contents) so it would be easy to find the patents.

I believe there are legal issues with storing the patents on public sites without permission. However, there is no law against listing their numbers and what they cover. I have a pile of about 10 of them in printed form from years ago. I printed them from the uspto.gov site and they are very useful.

Yeah, and suprisingly, they are quite accurate.

The MMC1 doc you mentioned (U.S.#4,949,298) did contain full schematics on the MMC1. There are 2 differences I noticed between the patent design, and the final one (as publically documented). The patent showed a MMC1 design where you have to send 7 bits to the MMC (instead of 5), where the extra 2 represent the register to be written to. Of course later, they must've realized that they could use the 2 address lines (A14 & A13) already going into the MMC for SRAM address decoding for immediate register selection.

The other difference was that the patent described a design where the 4th bit of the 4th register (PRG bank selection line A17) could control SRAM enabling (and using the 5th bit of reg 4 could then make line A17 impervious to the effects of the lorom/hirom bankswitching). However in practice, it was the high bit of the CHR address line (A16) that was used for SRAM enabling.

That said, it doesn't seem like any public documentation mentions a use for the 5th bit in reg 4. Considering that CHR A16 IS used to control SRAM enabling on some carts, you'd think that Nintendo would want to design the MMC so that the CHR A16 line could be made impervious to CHR bankswitching. But since the only carts that actually implemented the SRAM enable line were CHR-RAM containing carts (ones with no use for any kind of MMC-controlled bankswitching (SNROM)), they probably expected programmers to configure the MMC1 for 8K CHR bankswitching mode, so that the PPU's A12 line (pattern table selection) wouldn't interfere with the output of A16.

If anyone DOES know if the 5th bit of reg 4 is used for anything (if it actually does effect the PRG A17 line as described in the doc, or if it does somthing else, like control the CHR A16 line), please speak up.


The PPU patent document (U.S.#4,824,106) is also another good document. While it's may not be an easy read, it does give quite a detailed look at the internals of the PPU (block diagram of the whole thing, and schematics of the multiplexer). It appears that there is more than one patent for the PPU though (there are at least 2 more I know of). Does anyone know if there are any differences between these few PPU patent docs?


Also, does anyone know if Nintendo patented any hardware like the MMC2, MMC3, or 2A03 sound hardware? I've never seen them before, and was just wondering if anyone else had seen them.

The 5th bit of register 4 is what enables/disables SRAM (effectively goes directly to WRAM /CE).

--
Quietust
P.S. If you don't get this note, let me know and I'll write you another.

There are patents about MMC5 and many other interesting things: download http://nesdev.parodius.com/nesdevma.zip and do a search for something like "patents" or "US*". Anyway, why not making a list of all the patents we know and releasing it in nesdev site?

Patent documents are in the public domain, so there are no legal issues putting patent documents on a web page or whatever.

Regards,
-- Mark