The DMC channel has a 7-bit DAC which can be used directly by writing successive samples $4011 at the proper time interval.
The DMC can also play a 1-bit per sample delta-encoded sound sample automatically. Each successive bit specifies whether the current DAC value is incremented or decremented by 2. The resulting waveform is a stairstep, always going up or down (unless it's at the DAC's limit). The playback rate of a sound sample can be one of 16 predefined values which cover a few octaves.
Say you want to directly play a sample at 8kHz. Given a 1.79 MHz CPU clock rate, a sample must be output every 223.75 clocks. Since the interval between writes to $4011 can only be a whole number of clocks, it must vary between 223 and 224 clocks in the following pattern: 224, 224, 223, 224. The maximum error can always be kept within +/- 0.5 clocks.
A fixed point timer keeps track of the accumulating error and adds an extra cycle delay when the error warrants it. Fixed point refers to having a fixed division between the whole and fractional part of the number. Using the example above, one byte stores the whole part of the delay (223) and another the fractional part * 256 (0.75 * 256 = 192). The accumulated error is tracked to determine when an extra cycle delay needs to be added.
lda #223-overhead ; account for loop overhead
lda #192 ; 0.75
lda #128 ; start error at 0.5
clc ; accumulate error
adc fract ; carry set if error wraps around
bcs extra ; conditionally delay one extra cycle
; delay by 'whole' cycles
; write next sample to $4011
; loop while samples remain