I'm sorta confused by Brad's document about this. It seems any write to this register resets the frame counter and clock divider (of which I'm not comlpetely certain what that does?). But wouldn't that mean that if the game was strobing $4017 (because of a second player) that would drastically affect sound? And I guess it also controls IRQ generating. What is the purpose of the IRQ being generated?

If bit 6 of $4017 is 0 then a frame IRQ is generated slightly before the NMI (when the frame counter reaches zero....not sure when this is?) is generated (assuming interrupts are enabled) and bit 6 of $4015 is set right? What would be the point of this? I mean wouldn't the NMI go off slightly after the IRQ anyway?

Ummm, I guess my main questions are...

1) What is the frame counter (I don't exactly get Brad's description of it)?
2) What's the clock divider?
3) How do games use $4017 to synchronize their sound routine with the sound hardware (like what would they put in the interrupt routine)?
4) What do the clock divider and frame counter reset to when $4017 is written to?
5) What is the overall behavior of the clock divider and frame counter when they arn't reset via $4017 (do they reset themselves)?
6)And would strobing $4017 (for 2nd controller buttons) have a bad affect on the sound (or is it just values written to bits 6 and 7 that resets the counters)?

The answer is simple, really.
Writes to $4017 have NOTHING to do with controllers! Writes to $4016 strobe BOTH controllers.
I'll let someone else explain the sound stuff.

--
Quietust
P.S. If you don't get this note, let me know and I'll write you another.

See if the APU reference covers your questions: http://nesdev.parodius.com/apu_ref.txt

I'm not sure of the APU IRQ's purpose, since as you say there is already the ~60Hz NMI interrupt.

Post back if you have any further questions after reading the relevant section of the APU reference.

OK so....

"The frame sequencer contains a divider and a sequencer which clocks various
units.

The divider generates an output clock rate of just under 240 Hz, and appears to
be derived by dividing the 21.47727 MHz system clock by 89490. The sequencer is
clocked by the divider's output.

On a write to $4017, the divider and sequencer are reset, then the sequencer is
configured. Two sequences are available, and frame IRQ generation can be
disabled.

mi-- ---- mode, IRQ disable"

Mode is effectivly NTSC or PAL timing I guess and effects the divider by changing it (which means the sequencer changes also). And then IRQ disable disables the frame IRQ is it is set.


1) What is the frame counter (I don't exactly get Brad's description of it)?
A: It is the counter that cycles through the different functions of the sound....ok I still don't get this too well. Could you help me out?

2) What's the clock divider?
A: The clock divider divides the clock by a certain # (depending on bit 7 of $4017) and the frequency is then used by the sequencer to....sequence stuff. Right?

3) How do games use $4017 to synchronize their sound routine with the sound hardware (like what would they put in the interrupt routine)?
A: ....Uhhh, I guess the IRQ is generated, they poll bit 6 of $4015 to check if it's the frame IRQ. If it is it jsr's to it's sound routine? Ehhhh, I'll have to find some games that do this and try to figure them out....know any?

4) What do the clock divider and frame counter reset to when $4017 is written to?
A: The clock divider resets to whatever it needs to depending on bit 7, and the frame sequencer goes along with the divider, but I have no idea what it resets to.....?

5) What is the overall behavior of the clock divider and frame counter when they arn't reset via $4017 (do they reset themselves)?
A: They stay the same...? Well, I know the divider should stay the same, but what about the sequencer?

7)I guess my other question now is...how often does the frame irq occur?
A: It doesn't occur when bit 6 of $4017 is set, but it occurs slightly before the NMI (does it do so every frame or every 4 frames or something like that)?
---------------------------------------------------------------------------

"If the mode flag is clear, the 4-step sequence is selected, otherwise the
5-step sequence is selected and the sequencer is immediately clocked once.

f = set interrupt flag
l = clock length counters and sweep units
e = clock envelopes and triangle's linear counter

mode 0: 4-step effective rate (approx)
---------------------------------------
- - - f 60 Hz
- l - l 120 Hz
e e e e 240 Hz

mode 1: 5-step effective rate (approx)
---------------------------------------
- - - - - (interrupt flag never set)
l - l - - 96 Hz
e e e e - 192 Hz

At any time if the interrupt flag is set and the IRQ disable is clear, the
CPU's IRQ line is asserted."


1) The setting of the frame IRQ flag in $4015 does not happen in mode 5-step then? But it happens in mode 4-step. But then it only happens once every 4 frames as according to that chart? Do the frame IRQs still occur even though the flag isn't set?

A restatement of $4017 behavior from scratch seems the best approach here.

When $4017 is written with $00 or $40, the 4-step looping sequence is used. There is a 1/240 second delay before the first step of the sequence occurs, and a 1/240 second delay between each step.

step 1: clock envelopes and triangle's linear counter
step 2: clock envelopes, triangle's linear counter, length counters and sweep units
step 3: clock envelopes and triangle's linear counter
step 4: clock envelopes, triangle's linear counter, length counters and sweep units, and set interrupt flag
step 1: ...

Thus, the envelopes and triangle's linear counter are clocked at 240 Hz, the length counters and sweep units at 120 Hz, and the interrupt flag is set every 1/60 second.


When $4017 is written with $80 or $c0, the 5-step looping sequence is used. The first step of the sequence occurs immediately, with 1/240 second delay between each step.

step 1: clock envelopes, triangle's linear counter, length counters and sweep units
step 2: clock envelopes and triangle's linear counter
step 3: clock envelopes, triangle's linear counter, length counters and sweep units
step 4: clock envelopes and triangle's linear counter
step 5: do nothing
step 1: ...

Thus, the envelopes and triangle's linear counter are clocked 4 times every 5/240 second, which amounts to 192 Hz with uneven timing. The length counters and sweep units are clocked 2 times every 5/240 second, which amounts to 96 Hz with uneven timing. The interrupt flag is never set in this mode.


I'll have to add this to the things to rewrite whenever I make an update to the APU reference.

Reply if you have any further questions based on the above description.

Thank you!! :-) I get it now. The interrupt flag get's set on the last step which is just before the VBLANK interrupt. The sequencer goes through all the steps and it's speed varies depending on the clock divider. It does those 4-steps and then repeats thus alwys setting the flag right before VBLANK. So any write to $4017 then resets the sequencer back to step 1 and resets the divider to 5-step or 4-step.

Think you could produce any interesting sound effects with the register?

The interrupt flag get's set on the last step which is just before the VBLANK interrupt.

Assuming $4017 is written with $00 at the beginning of the VBL handler. The VBL interrupt occurs slightly less often than every 1/60 second, so the fourth step occurs slightly before the next VBL interrupt.

The sequencer goes through all the steps and it's speed varies depending on the clock divider.

The sequencer always runs each step for 1/240 second (240 Hz). It never changes speed. The only thing that varies is whether it uses the 4-step or 5-step sequence.

It does those 4-steps and then repeats thus alwys setting the flag right before VBLANK.

Again, this will only occur if it is synchronized (write $00 to $4017 every VBL). Otherwise it will occur earlier and earlier on successive VBL interrupts (since it runs slightly faster), finally overtaking the VBL and repeating the cycle.

So any write to $4017 then resets the sequencer back to step 1 and resets the divider to 5-step or 4-step.

Correct.

Think you could produce any interesting sound effects with the register?

Heh, not really since it doesn't directly output any sound.

OK, thanks a lot for your help :-) I think I fully understand it now. So I guess basically it's just for synchonization and you really can't use it for much else (unless you like kept reseting it or something).