1) Well, in fact, till now I've been using a quite inaccurate SP0 detection algorithm. SP0 flag was being set at the end of the scanline where the collision was occuring, so 114 or 113 CPU cycles were executed and then, if it was the case, SP0 flag was set. So I'll work on this point before moving to further accuracy research..

2&3) Don't worry about F-1 Race. The interlace demos I'm talking about are those showing bitmaps in a kind of high resolution. I dunno their real names: fdspic, a cool Zelda picture, a SMB3 one, etc..

4) Thanks, got it clear with Brad's doc.

Thanks for your reply ;)