|
The stuff is all mapped using the usual kind of address decoding. I used a 74hc139 for the WRAM and register mapping on my cart. You just hook an output from the decoder to the /CE on the chip to activate. The relevant address lines go to the inputs of the decoder, with PRG /CE AND M2 as the enable.
I haven't done anything like the 8kB PRG banks, 1kB CHR banks, etc. Not sure exactly.
> Generally speaking how do M2 based IRQ counters work? Which MMCs use 8/16bit counters?
I don't know what other mappers use them, but mine does. It just takes the 16bit value you write (8-bit would be way too small), inverts it, then increments it every time M2 is clocked until it overflows and generates an IRQ.
> Why is it necessary for MMCs to intercept data lines?
If you mean CHR data lines, I can't think of why.
> 113.75 clocks = 1 scanline?
Nope, it's 113.666
> Scanline based IRQ counters fire after how many CHR A12 toggles?
8.
> What does the PRG R/W pin do?
It's high when the NES is reading, low when it's writing. On my cart I inverted it to get an active-low read signal.
> Whats CIRAM on the cart connector?
To enable or disable the NES's internal VRAM. You can also muck around with the address lines to control the mirroring.
|
