The static RAM I've used required a particular sequence of chip select signals to properly transition from full-power to low-power retention mode. Thus some external controller is necessary for games with battery-backed SRAM. Special NVRAM modules with the controller and battery already built-in do exist, but their cost rules out their use in cartridges.
I made a development cartridge which used the save RAM to store my program (a modified Zelda board, which uses MMC1). I found that if the program was executing from the save RAM and I turned power off, various locations would get corrupted. I worked around this by copying the main loop of the code to the NES system RAM. Holding reset suspends the processor (and thus memory accesses), which is another way to avoid power-down while the save RAM is being accessed. This is my guess as to why holding reset avoids corruption. The save RAM controller could also be designed to handle a power-down at any time, and perhaps the MMC3 and later do this (I don't know if they do).
If the top loading NES doesn't have the data loss issue, perhaps it suspends the processor just before power is lost, achieving the same as described as above.