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SubjectThe PPU pixel pipeline  
Posted bytepples
Posted on4/9/04 2:48 PM
From IP68.54.20.186  



The "pixel pipeline" means that there are delays between writes to PPU ports and their effects on the screen because the PPU keeps some partially processed pixels in its registers. Hblank effects must be timed to take this into account, especially with respect to exactly when you turn on the sprite 0 collision flag. Some games even use mid-scanline effects, such as Pirates' CHR bankswitching or some MMC5 games' split-screen scrolling, which are most visibly affected.



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Entire Thread
Subject  Posted byPosted On
*Different implmentations..  Muchaserres4/9/04 1:55 PM
.*Re: Different implmentations..  tepples4/9/04 2:51 PM
..*Re: Different implmentations..  Muchaserres4/10/04 08:31 AM
...*Re: Different implmentations..  RoboNes4/10/04 08:40 AM
....*Re: Different implmentations..  <_Hyde_>4/10/04 8:37 PM
....*Re: Different implmentations..  Muchaserres4/10/04 08:54 AM
.*Re: Different implmentations..  Muchaserres4/9/04 2:04 PM
...The PPU pixel pipeline  tepples4/9/04 2:48 PM
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